The present invention relates to a (1+N) hitless channel switching system, in a (1+N) digital transmission system having N regular channels and a single standby channel, for switching one of the regular channels to the standby channel with non-interruption.
FIG. 1 is a block diagram showing a basic arrangement of a non-interruption regular/standby channel switching system generally used in radio digital transmission.
In FIG. 1, a transmitting side 100 is connected to a receiving side 200 through n regular channels represented by CH.sub.1 to CH.sub.n and a single standby channel represented by CH.sub.p.
The transmitting side 100 comprises: switches 11 having the same arrangement and provided to the regular channels CH.sub.1 to CH.sub.n to receive transmission signals IN.sub.1 to IN.sub.n ; multiplexers 12 having the same arrangement and provided to the regular channels CH.sub.1 to CH.sub.n and the standby channel CH.sub.p ; a pilot signal generator 16 for outputting a pilot signal; and a channel switching controller 18 for supplying a signal D to the switches 11 to control their switching operation.
When all the regular channels CH.sub.1 to CH.sub.n are normal, none of the switches 11 are switched. Therefore, the pilot signal is output from the pilot signal generator 16 to the channel CH.sub.p through a line 202.
If a fault occurs on one of the regular channels CH.sub.1 to CH.sub.n, e.g., the channel CH.sub.1, the switch 11 connected to the channel CH.sub.1 is switched in accordance with the control signal D supplied from the channel switching controller 18, and a transmission signal of the channel CH.sub.1 is supplied through the standby channel CH.sub.p.
The receiving side 200 comprises: channel monitors 13 for monitoring channel conditions of the standby channel CH.sub.p and the regular channels CH.sub.1 to CH.sub.n and outputting a standby channel condition signal B and regular channel condition signals A; demultiplexers 14 for demultiplexing the output signals from the channel monitors 13; switches 15 each for receiving the output signal from the demultiplexer 14 of the standby channel CH.sub.p at its one input terminal, receiving the output signal from a corresponding one of the demultiplexers 14 of the regular channels CH.sub.1 to CH.sub.n at its other input terminal, and selecting one of the input signals in accordance with a control signal E; a pilot signal detector 17 for detecting a pilot signal from the output signal from the demultiplexer 14 of the standby channel CH.sub.p ; and a channel switching controller 19 for outputting a switch control signal E for controlling the switches 15 in accordance with the standby channel condition signal B from the channel monitor 13 of the standby channel CH.sub.p, the regular channel condition signals A output from the channel monitors of the regular channels CH.sub.1 to CH.sub.n, and the output signal C from the pilot signal detector 17, and transmitting a signal F representing switching demand to the channel switching controller 18 of the transmitting side 100.
A switching sequence of hitless switching in FIG. 1 is generally performed as follows. That is, if a fault occurs on, e.g., the regular channel CH.sub.1, the channel monitor 13 of the channel CH.sub.1 supplies the signal A representing the fault to the channel switching controller 19. The channel switching controller 19 checks the presence/absence of the fault and the condition of the standby channel by using the standby channel condition signal B and the output signal C from the pilot signal detector 17 and then sends the switching demand signal to the channel switching controller 18 at the transmitting side 100. The channel switching controller 18 operates the switch 11 of the channel CH.sub.1 by the channel switching signal D.
The channel switching controller 19 at the receiving side 200 compares the transmission signal from the regular channel CH.sub.1 on which the fault occurs with the transmission signal from the standby channel. If it is determined that bits and phases of the two signals coincide with each other, the switching (hitless switching) signal E is supplied to the switch 15. The switch 15 switches its input from the demultiplexer 14 of the channel CH.sub.1 to the demultiplexer 14 of the standby channel CH.sub.p and outputs it as an output signal OUT1. As a result, switching from the channel CH.sub.1 on which the fault occurs is completed.
FIG. 2 is a block diagram showing a partial detailed arrangement of the system shown in FIG. 1 for monitoring channel quality by the parity check method which is conventionally often used.
At the transmitting side 100 shown in FIG. 2, a transmission signal output from the multiplexer 12 is supplied to an error correction calculator 1 and to a parity counter 4. A count obtained by the parity counter 4 is supplied to the multiplexer 12 and inserted in a predetermined time slot. The output signal of the multiplexer 12 is subjected to error correction processing of the error correction calculator 1 and then output to a channel CH.sub.j (j=1 to n).
At the receiving side 200 shown in FIG. 2, a signal subjected to error correction by an error correction circuit 2 is output to a demultiplexer 14 and a parity counter 5. The parity counter 5 performs parity counting similar to that of the parity counter 4 at the transmitting side 100 and outputs the count to a parity comparator 6. The demultiplexer 14 separates the parity inserted in the time slot by the multiplexer 12 at the transmitting side 100 and outputs the parity to the parity comparator 6. The parity comparator 6 compares the inputs from the parity counter 5 and the demultiplexer 14 and outputs a parity error signal based on the comparison result. A channel quality determination circuit 7 performs quality determination of the channel in accordance with the parity error signal and outputs the determination information to the channel switching controller 19.
However, since the channel quality monitoring using the parity bit in the conventional channel switching system is based on channel quality of a bit sequence after error correction, even if a large number of bit errors occur in the bit sequence before error correction, the bit errors of the bit sequence after error correction are maintained well. Therefore, according to the conventional method in which channel quality determination is performed by parity check after error correction, channel quality degradation caused by propagation path conditions cannot be detected in a short time period. In addition, as represented by a line AC in FIG. 4 showing an error rate characteristic before and after correction obtained when an error correction function is present, a degradation speed (speed of degradation in carrier wave power/noise ratio) is high, that is, for example, a time interval from an error rate 10.sup.-6 represented by a dotted line CL in FIG. 4 to system outage, e.g., an error rate 10.sup.-3 represented by a dotted line DL in FIG. 4 is short. Accordingly, a time usable for detecting information of channel degradation is short. As a result, system outage occurs before the transmission path is restored by channel switching.